CLASS

A class is an actual representation of an Abstrace data type. It therefore provides implementation details for the data structure used and operations. 

EXAMPLE:
  class A ;
      // attributes:
      int i

      // methods:
      task print    
  endclass

Definition (Class) : A class is the implementation of an abstract data type . It defines attributes and methods which implement the data structure and operations of the abstract data type, respectively. Instances of classes are called objects. Consequently, classes define properties and behaviour of sets of objects.

In SV classes also contain Constraints for randomization control.


Class Properties: 

 Instance Variables (Non-Static Fields) :
Technically speaking, objects store their individual states in "non-static fields", that is, fields declared without the static keyword. Non-static fields are also known as instance variables because their values are unique to each instance of a class (to each object, in other words); 

 Class Variables (Static Fields) : 
A class variable is any field declared with the static modifier; this tells the compiler that there is exactly one copy of this variable in existence, regardless of how many times the class has been instantiated. 

 Local Variables : 
Local Variables Similar to how an object stores its state in fields, a method will often store its temporary state in local variables. The syntax for declaring a local variable is similar to declaring a field (for example, int count = 0;). There is no special keyword designating a variable as local; that determination comes entirely from the location in which the variable is declared , which is between the opening and closing braces of a method. As such, local variables are only visible to the methods in which they are declared; they are not accessible from the rest of the class.

 Parameters : 
The important thing to remember is that parameters are always classified as "variables" not "fields". 

 Constants : 
Class properties can be made read-only by a const declaration like any other SystemVerilog variable. 

INTRODUCTION TO SYSTEMVERILOG

Hi Friends,

Today's topic going to cover a small introduction to SystemVerilog language. 

SystemVerilog is an Hardware Description Language and Hardware Verification Language. SV  based on extensions to Verilog. SystemVerilog was created by the donation of the Superlog language to Accellera in 2002. The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005 .

SystemVerilog language, which is a unified hardware design and verification language. 

The standard support below features:

1.  Behavioural hardware descriptions.

2.  Register transfer level (RTL) hardware descriptions.

3.  Gate-level hardware descriptions.

4.  Object-Oriented Testbench.

5.  Code coverage.

6.  Functional Coverage.

7. Constrained random constructs.

8. Application programming interfaces (APIs) for foreign programming languages.

Example:

Hello World Program:

module top;
  class example;
    task print();
      $display("Hello World");
    endtask
  endclass
  
  initial 
  begin
    example example_h;//Class type variable declared
    example_h = new();//Object of type example created
    example_h.print();
  end
endmodule

Result:

Hope this gives little overview about SystemVerilog Language.

Keep updating and keep sharing, Peace !!!

Thank You,
Moderator