INTRODUCTION TO SYSTEMVERILOG

Hi Friends,

Today's topic going to cover a small introduction to SystemVerilog language. 

SystemVerilog is an Hardware Description Language and Hardware Verification Language. SV  based on extensions to Verilog. SystemVerilog was created by the donation of the Superlog language to Accellera in 2002. The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005 .

SystemVerilog language, which is a unified hardware design and verification language. 

The standard support below features:

1.  Behavioural hardware descriptions.

2.  Register transfer level (RTL) hardware descriptions.

3.  Gate-level hardware descriptions.

4.  Object-Oriented Testbench.

5.  Code coverage.

6.  Functional Coverage.

7. Constrained random constructs.

8. Application programming interfaces (APIs) for foreign programming languages.

Example:

Hello World Program:

module top;
  class example;
    task print();
      $display("Hello World");
    endtask
  endclass
  
  initial 
  begin
    example example_h;//Class type variable declared
    example_h = new();//Object of type example created
    example_h.print();
  end
endmodule

Result:

Hope this gives little overview about SystemVerilog Language.

Keep updating and keep sharing, Peace !!!

Thank You,
Moderator