DATA TYPES

Hi Friends,

In this post we are going share list of data types in SystemVerilog Language. 

SystemVerilog extends Verilog by introducing C like data types, SystemVerilog adds new data types for better simulation and less memory. SystemVerilog adds a new 2-state data types that can only have bits with 0 or 1 values unlike verilog 4-state data types which can have 0, 1, X and Z.   SystemVerilog also allows user to define new data types.  


SystemVerilog 2-state data types can simulate faster, take less memory, and are preferred in some design styles. Then a 4-state value is automatically converted to a 2-state value, X and Z will be converted to zeros.

Signed And Unsigned : 

The data types byte, shortint, int, integer, and longint by default to signed. The data types bit, reg, and logic by default to unsigned.

To change types as unsigned or signed, user has to explicitly declare like below.

Example:

    int unsigned uint_variable;
    int signed sint_variable
    byte unsigned ubyte_variable;

User can also use cast feature to to change variable data type.

Example:     
    if (signed'(ubyte_variable)< 151) // ubyte_variable is unsigned


Void : 

The void data type represents nonexistent data. This type can be specified as the return type of functions to indicate no return value. 

Example:

module top;

  

  class example;

    function void print();//Function declared type void, which do not have a return value.

      $display("Hello World");

    endfunction

  endclass

  

  initial 

  begin

    example example_h;//Class type variable declared

    example_h = new();//Object of type example created

    example_h.print();

  end

  

endmodule 

Hope this article helps you.

Keep updating and keep sharing, Peace !!!

Thank You,
Moderator