Hi Friends,
This post will be covering array concept in systemverilog.
Systemverilog supports packed and un-packed arrays of data.
"Packed array" refer to the dimensions declared before identifier.
Example:
reg [0:3] array_variable;// 1-dimensional packed array
wire [31:0] [1:0] vari; // 2-dimensional packed array
"Un-packed array" refer to the dimension declared after identifier.
Example:
reg array_variable[0:3];// 1-dimensional unpacked array of integers
integer matrix[7:0][0:31][15:0]; // 3-dimensional unpacked array of integers
integer matrix[8][32][16]; // 3-dimensional unpacked array of integers
Fixed Arrays:
Fixed size array are created at compilation time. SystemVerilog accepts a single number, as an alternative to a range, to specify the size of an unpacked array. That is, [size] becomes the same as [0:size-1].
Example:
int Array[8][32]; is the same as: int Array[0:7][0:31];
Memories:
A one-dimensional array with elements of types reg, logic, or bit is also called a memory
Example:
logic [7:0] mema [0:255]; // declares a memory array of 256 8-bit
// elements. The array indices are 0 to 255
mema[5] = 0; // Write to word at address 5
data = mema[addr]; // Read word at address indexed by addr
Operations On Arrays
The following operations can be performed on all arrays, packed or unpacked:
1. Reading and writing the array, e.g., A = B
2. Reading and writing a slice of the array, e.g., A[i:j] = B[i:j]
3. Reading and writing a variable slice of the array, e.g., A[x+:c] = B[y+:c]
4. Reading and writing an element of the array, e.g., A[i] = B[i]
5. Equality operations on the array or slice of the array, e.g., A==B, A[i:j] != B[i:j]
Thank You,
Moderator.
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