CLASS

A class is an actual representation of an Abstrace data type. It therefore provides implementation details for the data structure used and operations. 

EXAMPLE:
  class A ;
      // attributes:
      int i

      // methods:
      task print    
  endclass

Definition (Class) : A class is the implementation of an abstract data type . It defines attributes and methods which implement the data structure and operations of the abstract data type, respectively. Instances of classes are called objects. Consequently, classes define properties and behaviour of sets of objects.

In SV classes also contain Constraints for randomization control.


Class Properties: 

 Instance Variables (Non-Static Fields) :
Technically speaking, objects store their individual states in "non-static fields", that is, fields declared without the static keyword. Non-static fields are also known as instance variables because their values are unique to each instance of a class (to each object, in other words); 

 Class Variables (Static Fields) : 
A class variable is any field declared with the static modifier; this tells the compiler that there is exactly one copy of this variable in existence, regardless of how many times the class has been instantiated. 

 Local Variables : 
Local Variables Similar to how an object stores its state in fields, a method will often store its temporary state in local variables. The syntax for declaring a local variable is similar to declaring a field (for example, int count = 0;). There is no special keyword designating a variable as local; that determination comes entirely from the location in which the variable is declared , which is between the opening and closing braces of a method. As such, local variables are only visible to the methods in which they are declared; they are not accessible from the rest of the class.

 Parameters : 
The important thing to remember is that parameters are always classified as "variables" not "fields". 

 Constants : 
Class properties can be made read-only by a const declaration like any other SystemVerilog variable. 

INTRODUCTION TO OBJECT ORIENTED PROGRAMMING

Hi Friends,

Yet another post on oop's. Hope it helps you'll.

The OOP programming model programs are organised around "objects" and "data". Objects represent some things and like any other objects in the real Objects, in programming language have certain behaviour, properties, type, and identity. In OOP based language the principal aim is to find out the objects to manipulate and their relation between each other. OOP in systemverilog  offers greater flexibility and compatibility then procedural language like verilog. 

Understanding of "Objects" are key to object-oriented technology. Look around right now and you'll find many examples of real-world objects: your PC, your table, your chair.

Real-world objects share two characteristics: They all have state and behaviour. System have state (name, colour) and behaviour (playing music,switch on & off). Identifying the state and behaviour for real-world objects is a great way to begin thinking in terms of object-oriented programming. 

SystemVerilog is a object oriented programming  and to understand the functionality of OOP in SystemVerilog, we first need to understand several fundamentals related to objects. These include class, method, inheritance, encapsulation, abstraction, polymorphism etc.

Class 

 It is the building point of OOP and that contains data and codes with . In SystemVerilog OOPS , everything happens within class and it describes a set of objects with common behaviour. The class definition describes all the properties, behaviour, and identity of objects present within that class.    

Example:

Class example;
----------
----------
endclass

Object 

 Objects are the actual unit of object orientation concept with behaviour, identity. An object is expressed by the variable and methods within the objects. Again these variables and methods are distinguished from each other as instant variables, instant methods and class variable and class methods. 

Example:

Example ex_h;
ex_h = new();//Creates object of type Example and assigned object handle to variable "ex_h".


Methods 

 We know that a class can define both attributes "Variables" and behaviours "Methods". Again attributes are defined by variables and behaviours are represented by methods. In other words, methods define the abilities of an object. 


Inheritance 

 This is the mechanism of organising and structuring program. Though objects are distinguished from each other by some additional features but there are objects that share certain things common. In object oriented programming classes can inherit some common behaviour and state from others. Inheritance in OOP allows to define a general class and later to organise some other classes simply adding some details with the old class definition. This saves work as the special class inherits all the properties of the old general class and as a programmer you only require the new features. This helps in a better data analysis, accurate coding and reduces development time. In Verilog , to write a new definition using the existing definition is done inserting `ifdef compilation controls into the existing code.  


Abstraction 

 The process of abstraction in SystemVerilog is used to hide certain details and only show the essential features of the object. In other words, it deals with the outside view of an object. 


Encapsulation 

 This is an important programming concept that assists in separating an object's state from its behaviour. This helps in hiding an object's data describing its state from any further modification by external component. In SystemVerilog there are three different terms used for hiding data constructs and these are public, private and protected . As we know an object can associated with data with predefined classes and in any application an object can know about the data it needs to know about. So any unnecessary data are not required by an object can be hidden by this process. It can also be termed as information hiding that prohibits outsiders in seeing the inside of an object in which abstraction is implemented.  


Polymorphism 

 It describes the ability of the object in belonging to different types with specific behaviour of each type. So by using this, one object can be treated like another and in this way it can create and define multiple level of interface. Here the programmers need not have to know the exact type of object in advance and this is being implemented at run time. 

We will discuss above three concepts in details in up-coming posts.

Thank You,
Moderator

ARRAYS

Hi Friends,

This post will be covering array concept in systemverilog. 

Systemverilog supports packed and un-packed arrays of data. 

"Packed array" refer to the dimensions declared before identifier.

Example:

reg [0:3] array_variable;// 1-dimensional packed array

wire [31:0] [1:0] vari; // 2-dimensional packed array

"Un-packed array" refer to the dimension declared after identifier. 

Example:

reg array_variable[0:3];// 1-dimensional unpacked array of integers

integer matrix[7:0][0:31][15:0]; // 3-dimensional unpacked array of integers

integer matrix[8][32][16]; // 3-dimensional unpacked array of integers 

  

An array hold a fixed number of equally-sized data elements. Individual elements are accessed by index using a consecutive range of integers.  Some type of arrays allows to access individual elements using non consecutive values of any data types.  Arrays can be classified as fixed-sized arrays (sometimes known as static arrays) whose size cannot change once their declaration is done, or dynamic arrays, which can be resized. 

Fixed Arrays: 

Fixed size array are created at compilation time. SystemVerilog accepts a single number, as an alternative to a range, to specify the size of an unpacked array. That is, [size] becomes the same as [0:size-1]. 

Example:

   int Array[8][32]; is the same as: int Array[0:7][0:31];

Memories:

A one-dimensional array with elements of types reg, logic, or bit is also called a memory

  
Example:
    

logic [7:0] mema [0:255]; // declares a memory array of 256 8-bit

                                          // elements. The array indices are 0 to 255

mema[5] = 0; // Write to word at address 5

data = mema[addr]; // Read word at address indexed by addr

Operations On Arrays 

The following operations can be performed on all arrays, packed or unpacked:
1. Reading and writing the array, e.g., A = B

2. Reading and writing a slice of the array, e.g., A[i:j] = B[i:j]

3. Reading and writing a variable slice of the array, e.g., A[x+:c] = B[y+:c]

4. Reading and writing an element of the array, e.g., A[i] = B[i]

5. Equality operations on the array or slice of the array, e.g., A==B, A[i:j] != B[i:j]

Thank You,

Moderator.

INTRODUCTION TO SYSTEMVERILOG

Hi Friends,

Today's topic going to cover a small introduction to SystemVerilog language. 

SystemVerilog is an Hardware Description Language and Hardware Verification Language. SV  based on extensions to Verilog. SystemVerilog was created by the donation of the Superlog language to Accellera in 2002. The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005 .

SystemVerilog language, which is a unified hardware design and verification language. 

The standard support below features:

1.  Behavioural hardware descriptions.

2.  Register transfer level (RTL) hardware descriptions.

3.  Gate-level hardware descriptions.

4.  Object-Oriented Testbench.

5.  Code coverage.

6.  Functional Coverage.

7. Constrained random constructs.

8. Application programming interfaces (APIs) for foreign programming languages.

Example:

Hello World Program:

module top;
  class example;
    task print();
      $display("Hello World");
    endtask
  endclass
  
  initial 
  begin
    example example_h;//Class type variable declared
    example_h = new();//Object of type example created
    example_h.print();
  end
endmodule

Result:

Hope this gives little overview about SystemVerilog Language.

Keep updating and keep sharing, Peace !!!

Thank You,
Moderator

DATA TYPES

Hi Friends,

In this post we are going share list of data types in SystemVerilog Language. 

SystemVerilog extends Verilog by introducing C like data types, SystemVerilog adds new data types for better simulation and less memory. SystemVerilog adds a new 2-state data types that can only have bits with 0 or 1 values unlike verilog 4-state data types which can have 0, 1, X and Z.   SystemVerilog also allows user to define new data types.  


SystemVerilog 2-state data types can simulate faster, take less memory, and are preferred in some design styles. Then a 4-state value is automatically converted to a 2-state value, X and Z will be converted to zeros.

Signed And Unsigned : 

The data types byte, shortint, int, integer, and longint by default to signed. The data types bit, reg, and logic by default to unsigned.

To change types as unsigned or signed, user has to explicitly declare like below.

Example:

    int unsigned uint_variable;
    int signed sint_variable
    byte unsigned ubyte_variable;

User can also use cast feature to to change variable data type.

Example:     
    if (signed'(ubyte_variable)< 151) // ubyte_variable is unsigned


Void : 

The void data type represents nonexistent data. This type can be specified as the return type of functions to indicate no return value. 

Example:

module top;

  

  class example;

    function void print();//Function declared type void, which do not have a return value.

      $display("Hello World");

    endfunction

  endclass

  

  initial 

  begin

    example example_h;//Class type variable declared

    example_h = new();//Object of type example created

    example_h.print();

  end

  

endmodule 

Hope this article helps you.

Keep updating and keep sharing, Peace !!!

Thank You,
Moderator